Dual-mode switching dc-to-dc converter

ABSTRACT

A transformer has a primary winding connected to a pair of DC input terminals via an active switch, and a secondary winding connected to a pair of DC output terminals via a first rectifying and smoothing circuit. The active switch is driven constantly under normal load, and at intervals under light load, under the direction of a switch control circuit. This switch control circuit is powered with a control voltage fed from a second rectifying and smoothing circuit which is connected to a tertiary winding of the transformer. In order to preclude malfunctioning or nonoperation in the event of an abnormal drop of the control voltage during operation in light load mode, the switch control circuit is equipped to drive the active switch at shorter intervals in control voltage recovery mode when the control voltage falls below a predefined limit than the normal intervals of the light load mode.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of Application PCT/JP2004/019554, filed Dec. 27,2004, which claims priority to Japanese Patent Application No.2004-007253 filed Jan. 14, 2004.

BACKGROUND OF THE INVENTION

This invention relates to switching-mode DC-to-DC converters, and moreparticularly to those of the dual-mode variety capable of driving, orrapidly turning on and off, the active switch constantly under normalload and at temporarily enforced intervals under light load.

A typical conventional switching-mode DC-to-DC converter includes atransformer having a primary winding coupled to the pair of DC inputterminals via an active switch, and a secondary winding coupled to thepair of DC output terminals via a rectifying and smoothing circuit. Theactive switch is driven by a switch control circuit which is poweredfrom a tertiary winding of the transformer via another rectifying andsmoothing circuit.

It has been suggested in conjunction with the DC-to-DC converter of thekind outlined above to drive the active switch at intervals when thepower requirement of the load is low, in order to reduce switching lossand hence to enhance the efficiency of the converter. The intermittentdriving of the active switch in light load mode makes the switchingsdrastically less in number on an average per unit length of time thanwhen the switch is driven continuously in normal load mode. Thediminution of average switchings in light load mode leads to thecurtailment of switching loss and consequently to a higher overallefficiency of the converter.

Such dual-mode driving of the voltage regulator switch has had aweakness left undefeated, however. The voltage across the smoothingcapacitor of the first recited rectifying and smoothing circuit, on theoutput side of the transformer, rises when the active switch is beingdriven, and diminishes when it is not. The same applies to the supplyvoltage (herein termed the control voltage) fed from the secondrectifying and smoothing circuit coupled to the transformer tertiary tothe switch control circuit for powering the latter.

A problem arose because of a difference in the rate of voltagediminution between the capacitor of the first rectifying and smoothingcircuit and that of the second rectifying and smoothing circuit when thepower requirement of the load was extremely low. The power requirementof the switch control circuit is hardly affected by changes in the powerrequirement of the load, so that the capacitor voltage of the secondrectifying and smoothing circuit declines far more greatly than that ofthe first rectifying and smoothing circuit while the active switch isnot being driven during operation in light load mode. Actually, theswitch control circuit went out of operation, becoming totally incapableof driving the active switch, in the worst case where the controlvoltage being supplied to the switch control circuit fell below theallowable minimum.

Once set out of operation, the switch control circuit must return tonormal functioning after a mandatory restart period of several hundredsmilliseconds. The smoothing capacitor was left uncharged during thisrestart period, so that its voltage dwindled further, making itimpossible or difficult to feed the load as required.

It might be contemplated for the mitigation of the foregoing difficultyto provide a transformer tertiary of a greater number of turns, and asmoothing capacitor of greater capacitance, than heretofore. Such atransformer would introduce a greater power loss, running counter to theprime objective of overall converter efficiency enhancement. Anotherpossible measure might be to drive the active switch at shorterintervals throughout the light load mode. This remedy is objectionablebecause it would make the average number of switchings greater per unitlength of time, again to the impairment of the noted prime objective.

A more drastic approach is suggested by Japanese Unexamined PatentPublication No. 2003-33018, which calls for invalidation of the lightload mode altogether in the event of an excessive drop in the controlvoltage supplied to the switch control circuit. The active switch isdriven continuously even when it should be at intervals, thereby givingrise to as much switching loss under light load as under normal load.

SUMMARY OF THE INVENTION

The present invention seeks, in a dual-mode DC-to-DC converter of thekind defined, to assure stable operation of the converter in the face ofa drop in the control voltage being fed to the switch control circuit inlight load mode, while at the same time a resulting increase inswitching loss is kept at a minimum.

Briefly, the invention may be summarized as a dual-mode switchingDC-to-DC converter capable of operation in either normal load mode orlight load mode depending upon the power requirement of the load.Included are an active switch connected to DC input means via atransformer, a switch control circuit for controllably driving theactive switch, a first rectifying and smoothing circuit connectedbetween the transformer and DC output means for providing a DC outputvoltage to be applied to a load, and a second rectifying and smoothingcircuit connected between the transformer and the switch control circuitfor supplying a control voltage to the latter.

Of the above listed components of the DC-to-DC converter, characterizingthe invention is the switch control circuit which comprises: (a)feedback circuit means for providing a feedback signal indicative of theDC output voltage; (b) a control voltage monitoring circuit connected tothe second rectifying and smoothing circuit for providing an outputsignal indicative of whether the control voltage is less than apredefined limit or not; (c) a switch control pulse generator circuitconnected between the feedback circuit means and the active switch forgenerating switch control pulses thereby to drive the active switch soas to keep the DC output voltage constant; (d) a multiple referencevoltage generator circuit connected to the control voltage monitoringcircuit for providing a multiple-value reference voltage that has eitherof first two different predefined values when the control voltage is notless than the predefined limit and that has either of second twodifferent predefined values when the control voltage is less than thepredefined limit, the second two different predefined values beingintermediate the first two different predefined values; and (e) a modeselect comparator having a first input connected to the feedback circuitmeans, a second input connected to the multiple reference voltagegenerator circuit, and an output connected to the switch control pulsegenerator circuit. The mode select comparator operates hysteretically inresponse to the multiple-value reference signal in order to cause theswitch control pulse generator circuit to drive the active switch atfirst predetermined intervals when the power requirement of the load isrelatively low and, at the same time, when the control voltage is notless than the predefined limit, and at second predetermined intervals,shorter than the first predetermined intervals, when the powerrequirement of the load is relatively low and, at the same time, whenthe control voltage is less than the predefined limit.

Thus, when the DC-to-DC converter is triggered into light load mode,with the control voltage initially higher than the predefined limit forpowering the switch control circuit, the multiple reference voltagegenerator circuit provides the reference voltage that has the first twodifferent predefined values. Operating hysteretically in response tothese first two different reference voltage values, the mode selectcomparator causes the switch control pulse generator circuit to drivethe active switch at relatively long intervals in light load mode.

The control voltage may diminish below its allowable minimum during thislight load mode operation, as has been explained in connection with theprior art. Thereupon the multiple reference voltage generator circuitprovides the reference voltage that has the second two differentpredefined values. Both being intermediate the first two differentreference voltage values, the second two different reference voltagevalues have a difference therebetween that is less than that between thefirst two. The mode select comparator responds to these second twodifferent reference voltage values by causing the switch control pulsegenerator circuit to drive the active switch at shorter intervals (inwhat is herein termed the control voltage recovery mode) than those inlight load mode. During subsequent operation in control voltage recoverymode overriding the light load mode, the control voltage will recover toits normal value, or to a value more or less close to it, therebymaintaining the switch control circuit in operation.

It will be appreciated that the active switch is driven intermittentlynot only when the DC output voltage falls below a prescribed limit butadditionally when the control voltage grows less than its allowableminimum. Thus, compared to the prior art where the active switch isdriven continuously in the event of an excessive drop in the controlvoltage, the invention succeeds in reduction of the average number ofswitchings per unit length of time and so contributes to enhancement ofthe efficiency of switching-mode power supplies of this kind.

The above and other objects, features and advantages of this inventionwill become more apparent, and the invention itself will best beunderstood, from a study of the following description and appendedclaims, with reference had to the attached drawings showing somepreferable embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic electrical diagram, partly in block form, of thedual-mode switching DC-to-DC converter embodying the principles of thisinvention.

FIG. 2 is a schematic electrical diagram showing in more detail theswitch control circuit included in the DC-to-DC converter of FIG. 1.

FIG. 3, consisting of (A) through (F), is a diagram of waveforms usefulin explaining the operation of the DC-to-DC converter of FIGS. 1 and 2in normal load mode.

FIG. 4, consisting of (A) through (F), is a waveform diagram similar toFIG. 3 and useful in explaining the operation of the DC-to-DC converterof FIGS. 1 and 2 immediately before being triggered into light loadmode.

FIG. 5, consisting of (A) through (F), is a diagrams of waveformsappearing at various parts of the switch control circuit of FIG. 2 innormal load mode, light load mode, and control voltage recovery mode.

FIG. 6 is a diagram similar to FIG. 1 but showing another preferredembodiment of the invention.

FIG. 7 is a schematic electrical diagram of a modification of the modeselect circuit in the DC-to-DC converter of FIG. 1.

FIG. 8 is a partial schematic electrical diagram of another modificationof the switch control circuit in the DC-to-DC converter of FIG. 1.

FIG. 9, consisting of (A) through (C), is a diagram of waveformsappearing at various parts of the modified switch control circuit ofFIG. 8.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention is currently believed to be best embodied in thedual-mode, flyback DC-to-DC converter depicted in its entirety in FIG. 1of the drawings above. The representative DC-to-DC converter is broadlydivisible into a DC-to-DC converter circuit 1 and a switch controlcircuit 2, the latter being shown in more detail in FIG. 2. Withreference to FIG. 1 the DC-to-DC converter circuit 1 comprises:

1. A pair of DC input terminals 4 and 5 shown connected to a DC powersupply 3.

2. A pair of DC output terminals 11 and 12 shown connected to a load 15.

3. A transformer 6 having a primary winding N₁ connected to the pair ofDC input terminals 4 and 5, a secondary winding N₂ connected to the pairof DC output terminals 11 and 12, and a tertiary winding N₃.

4. An active switch 7 connected between the pair of DC input terminals 4and 5 via the transformer primary N₁ for rapidly switching the DC inputvoltage under the direction of the switch control circuit 2.

5. A first rectifying and smoothing circuit 9 connected to thetransformer secondary N₂ for providing a DC output voltage.

6. A second rectifying and smoothing circuit 10 connected to thetransformer tertiary N₃ for providing a DC control voltage V_(cc) whichis fed to the switch control circuit 2 for powering the same.

In practice the DC power supply 3 may be either a rectifying andsmoothing circuit or a battery. It applies a prescribed DC voltagebetween the pair of DC input terminals 4 and 5.

The transformer 6 has the noted three windings N₁, N₂ and N₃ all coiledaround a magnetic core 14 and all electromagnetically coupled together.The transformer primary N₁ has its pair of opposite extremitiesconnected respectively to the pair of DC input terminals 4 and 5.Interposed between the DC input terminal 5, which is grounded, and thetransformer primary N₁ is the active switch 7 which takes the form of acontrollable solid-state switch such as a field-effect transistor. Acurrent detect resistor 8 is connected between the grounded DC inputterminal 5 and the active switch 7 for providing a current detect signalV_(i) in the form of a sawtoothed voltage indicative of the magnitude ofthe current flowing through the transformer primary N₁ and active switch7.

The transformer secondary N₂ is connected to the first rectifying andsmoothing circuit 9 and thence to the pair of DC output terminals 11 and12. The first rectifying and smoothing circuit 9 comprises a diode D₁and a smoothing capacitor C₁. The smoothing capacitor C₁ is connected inparallel with the transformer secondary N₂ via the diode D₁ and to thepair of DC output terminals 11 and 12. The load 15 may make variablepower requirement which for the purposes of this invention may bedescribed as normal or low depending upon whether it is higher or lowerthan a predetermined limit.

The second rectifying and smoothing circuit 10 also comprises a diode D₂and a smoothing capacitor C₂. The smoothing capacitor C₂ is connected inparallel with the transformer tertiary N₃ via the diode D₂. Thesmoothing capacitor C₂ has one terminal connected both to the DC inputterminal 4 via a startup resistor 13 and to the plus supply terminal 16_(a) of the switch control circuit 2. The other terminal of thesmoothing capacitor C₂ and the ground terminal 16 _(b) of the switchcontrol circuit 2 are both connected to the DC input terminal 5.

The switch control circuit 2 possesses the following functions:

1. Monitoring the DC output voltage.

2. Causing the active switch 7 to be driven constantly in normal loadmode when the power requirement of the load 15 is higher than theprescribed limit.

3. Causing the active switch 7 to be driven at intervals in light loadmode when the power requirement of the load is less than the prescribedlimit.

4. Monitoring the output voltage of the second rectifying and smoothingcircuit 10.

5. Causing the active switch 7 to be driven at shorter intervals incontrol voltage recovery mode than those in light load mode when thecontrol voltage being fed from the second rectifying and smoothingcircuit 10 to the switch control circuit 2 falls below a predeterminedvalue.

For performing these functions the switch control circuit 2 comprisesthe following four circuits shown in block form in FIG. 1 and in detailin FIG. 2:

1. An output voltage detector circuit 17 for providing an optical outputindicative of the DC output voltage being applied to the load 15.

2. A switch control pulse generator circuit 18 for providing a series ofswitch control pulses thereby to drive the active switch 7 in responseto the current detect signal V_(i) and the optical output from theoutput voltage detector circuit 17.

3. A mode selector circuit 19 responsive to an output voltage feedbacksignal V_(f) from the switch control pulse generator circuit 18 forcausing the same to drive the active switch 7 either constantly innormal load mode, at intervals in light load mode, or at shorterintervals in control voltage recovery mode.

4. A control voltage monitoring circuit 20 for monitoring the controlvoltage V_(cc) from the second rectifying and smoothing circuit 10 bycomparing the control voltage with a predefined value.

With continued reference to FIG. 1 the output voltage detector circuit17 is connected to the pair of DC output terminals 11 and 12 by way ofconductors 21 and 22. This circuit 17 includes a light-emitting diode(LED) 34 for putting out an optical signal of variable intensityindicative of the magnitude of the DC output voltage.

Electrically isolated from the output voltage detector circuit 17, theswitch control pulse generator circuit 18 incorporates a photoreceptor41 for inputting the optical output therefrom. Additionally, the switchcontrol pulse generator circuit 18 has an input connected to the currentdetect resistor 8 by way of a conductor 23 and an output connected tothe control terminal of the active switch 7. The current detect resistor8 is shown outside the switch control pulse generator circuit 18 forillustrative convenience only. This resistor 8 might be considered apart of the switch control pulse generator circuit 18.

Having an input connected to the switch control pulse generator circuit18 by way of a conductor 25, the mode selector circuit 19 determines thepower requirement of the load 15 from the output voltage feedback signalV_(f) which has been reconstructed in the circuit 18 from the opticaloutput from the output voltage detector circuit 17. When the powerrequirement is found low, the mode selector circuit 19 delivers a modeselect signal over a conductor 28 to the switch control pulse generatorcircuit 18, such that the active switch 7 is thereby driven atintervals.

The control voltage monitoring circuit 20 has an input connected to theplus supply terminal 16 _(a) of the switch control circuit 2 by way of aconductor 26 and an output connected to the mode selector circuit 19 byway of a conductor 27. The output from this control voltage monitoringcircuit 20 is a binary signal indicative of whether the control voltageV_(cc) is higher than a predetermined limit or not.

Reference is now invited to FIG. 2 for a more detailed study of theswitch control circuit 2. The waveform diagrams of FIGS. 3-5 will alsobe referred to in the course of the detailed inspection of FIG. 2. FIG.3 depicts signals appearing at various parts of the DC-to-DC converterof FIGS. 1 and 2 in normal load mode; FIG. 4 the same signalsimmediately before the converter is ushered into light load mode; andFIG. 5 the signals appearing at various parts of the converter duringoperation in normal load mode, light load mode, and control voltagerecovery mode according to the invention.

The switch control circuit 2 includes as aforesaid the output voltagedetector circuit 17 which comprises two voltage-dividing resistors 29and 30 interconnected in series between the pair of DC output terminals11 and 12, FIG. 1., via the conductors 21 and 22. The junction betweenthese resistors 29 and 30 is connected to the base of an npn transistor31. This transistor 31 has an emitter connected to the conductor 22 viaa reference voltage source such as a zener diode 32, and a collectorconnected to the conductor 21 via a current limiting resistor 33 and alight source such as the aforementioned LED 34. The transistor 31functions as a differential amplifier, causing the flow through the LED34 of a current having a magnitude proportional to the differencebetween the reference voltage from its source 32 and a prescribedfraction of the DC output voltage between the conductors 21 and 22. TheLED 34 emits light with an intensity proportional to the DC outputvoltage between the conductors 21 and 22. This optical output of theoutput voltage detector circuit 17 is input to the switch control pulsegenerator circuit 18.

The switch control pulse generator circuit 18 includes a clock oroscillator 35 which generates a series of accurately timed pulses, seenat (B) in both FIGS. 3 and 4 and at (A) in FIG. 5, with a recurrencerate in the range of 20-100 kilohertz. The clock pulses are directedthrough an AND gate 37 to the set input S of an RS flip-flop 36. Thisflop-flop has a reset input R connected to a comparator 40.Consequently, set by each clock pulse 35 and reset by the output fromthe comparator 40, the flip-flop 36 puts out rectangular pulses ofvariable duration indicated at (C) in both FIGS. 3 and 4.

For selectively blocking the clock pulses before delivery to theflip-flop 36, the AND gate 37 has another input connected to the modeselector circuit 19 by way of the conductor 28. As seen at (D) in FIG.5, the mode select signal V₄₄ fed from the mode selector circuit 19 overthe conductor 28 is such that the AND gate 37 puts out pulses V₃₇ eitherat a fixed rate (normal load. mode), as before t₁ in FIG. 5, atrelatively long intervals (light load mode) as from t₁ to t₆ in the samefigure, or at shorter intervals (control voltage recovery mode) as fromt₆ to t₇ in the same figure.

The flip-flop 36 has its noninverting output Q connected to a switchdriver circuit 38 and thence to the control input of the active switch 7by way of the conductor 24. It is understood that the switch controlpulses from the switch driver circuit 38 are applied between the gateand source of the active switch 7. The electrical connection between theswitch driver circuit 38 and the source of the active switch 7 is notshown for simplicity.

The noted output voltage detector circuit 17 is optically coupled to afeedback circuit 39, shown included in the switch control pulsegenerator circuit 18, for creating a feedback signal V_(f) in inverseproportion to the DC output voltage. The feedback circuit 39 includes aphototransistor 41 which is to be irradiated by the LED 34 of the outputvoltage detector circuit 17. The phototransistor 41 has its collectorconnected to one terminal of a biasing power supply 43 via a resistor 42and its emitter connected to the other terminal of that power supply.Thus the phototransistor 41 provides the feedback signal V_(f) ininverse proportion to the voltage between the pair of DC outputterminals 11 and 12, FIG. 1.

The junction P₁ between the phototransistor 41 and the resistor 42 isconnected to the minus input of the comparator 40. The plus input ofthis comparator 40 is connected by way of the conductor 23 to thejunction between the active switch 7, FIG. 1, and the current detectresistor 8 for receiving the current detect signal V_(i).

At (E) in FIG. 3 are indicated the feedback signal V_(f) and currentdetect signal V_(i) which are both input as above to the comparator 40.The ramps of the current detect signal V_(i) are synchronized with theconducting periods of the active switch 7. The comparator 40 goes highwhen each current detect signal ramp reaches the feedback signal V_(f),thereby resetting the flip-flop 36. It is thus seen that, as depicted at(C) in both FIGS. 3 and 4, the flip-flop 36 is set as at t₁ and reset att₂. The flip-flop 36 completes one cycle of operation when it is againset at t₃, and thereafter repeats the same cycle.

The output voltage of the DC-to-DC converter rises with a drop in powerconsumption by the load 15, resulting in a decrease in the voltagefeedback signal V_(f) at the junction P₁ of the feedback circuit 39. Thefeedback signal V_(f) is shown to be lower in value at (E) in FIG. 4than at (E) in FIG. 3. Having the sawtoothed or triangular waveform onaccount of the inductance of the transformer primary N₁, the currentdetect signal V_(i) will build up to the level of the feedback signalV_(f) in a shorter period of time when the latter signal has a lowervalue as at (E) in FIG. 4. The output pulses of the flip-flop 36 willtherefore grow less in duration as at (C) in FIG. 4 with a decline inthe power requirement of the load 15. As the switch control pulses thusdiminish in duty ratio, the DC output voltage will lower to the requiredlevel.

Referring once again to FIG. 2, the mode selector circuit 19 is broadlydivisible into a comparator 44 and a multiple reference voltagegenerator circuit 45. This comparator 44 will be hereinafter referred toas the mode select comparator in contradistinction from the comparator40 of the switch control pulse generator circuit 18, and the lattercomparator 40 as the switch control comparator. The mode selectcomparator 44 has its plus input connected by way of the conductor 25 tothe junction P₁ of the feedback circuit 39 and its minus input to themultiple reference voltage generator circuit 45. The output of the modeselect comparator 44 is connected to the AND gate 37 of the switchcontrol pulse generator circuit 18 for delivery of the mode selectsignal V₄₄ over the conductor 28.

Designed to provide a reference voltage V_(r) of multiple levels V₁, V₂,V₃ and V₄ all seen at (C) in FIG. 5, for hysteretic operation of themode select comparator 44, the multiple reference voltage generatorcircuit 45 comprises:

1. A serial circuit of a first switch S₁, first resistor R₁ and firstreference voltage source 46 which is connected between the minus inputof the mode select comparator 44 and the ground terminal 16 _(b).

2. A serial circuit of a second switch S₂, second resistor R₂ and secondreference voltage source 47 which also is connected between the minusinput of the mode select comparator 44 and the ground terminal 16 _(b).

3. A serial circuit of a third switch S₃ and third resistor R₃ which isconnected in parallel with the serial circuit of the first resistor R₁and first reference voltage source 46.

4. A serial circuit of a fourth switch S₄ and fourth resistor R₄ whichis connected in parallel with the serial circuit of the second resistorR₂ and second reference voltage source 47.

The first switch S₁ has its control terminal connected to the output ofthe mode select comparator 44 thereby to be turned on when thecomparator output indicates the driving of the active switch 7. Thesecond switch S₂ also has its control terminal connected to the modeselect comparator 44, but via an inverter 48, in order to be turned onwhen the comparator output indicates the non-driving of the activeswitch 7. The third switch S₃ has its control terminal connected to theoutput conductor 27 of the control voltage monitoring circuit 20 via aninverter 49 in order to be turned on when the output from the controlvoltage monitoring circuit is low. The fourth switch S₄ has its controlterminal connected directly to the output conductor 27 of the controlvoltage monitoring circuit 20 in order to be turned on when the outputfrom the control voltage monitoring circuit is high.

Thus the multiple reference voltage generator circuit 45 delivers thereference voltage V_(r) having any of the four different V₁- V₄ to themode select comparator 44. The first and second reference voltagesources 46 and 47 provide the second and fourth reference voltages V₂and V₄, respectively.

Constituting a feature of this invention, the control voltage monitoringcircuit 20 comprises a hysteretic comparator (hereinafter referred to asthe control voltage comparator) 51 and a reference voltage source 52.The control voltage comparator 51 has its minus input connected to thesupply terminal 16 _(a) of the switch control circuit 2 and thence tothe smoothing capacitor C₂, FIG. 1, of the second rectifying andsmoothing circuit 10, and its plus input connected to the referencevoltage source 52. The output of the control voltage comparator 51 isconnected to the multiple reference voltage generator circuit 45 of themode selector circuit 19 by way of the output conductor 27.

The reference voltage V₅₂ from its source 52 has a value that is eitherequal to the minimum allowable value of the control voltage V_(cc) orbetween this minimum allowable value and the normal value of the controlvoltage V_(cc). That is to say that the reference voltage V₅₂ has avalue higher than the maximum control voltage at which the switchcontrol circuit 2 becomes incapable of operation.

At (E) in FIG. 5 is shown the control voltage V_(cc) to be higher thanthe reference voltage V₅₂, the lower trip point (LTP) of the hystereticcontrol voltage comparator 51, until t6. The resulting output V₅₁ fromthe control voltage comparator 51 is therefore low until that moment, asat (F) in FIG. 5. The low comparator output closes the third switch S₃,and opens the fourth switch S₄, of the multiple reference voltagegenerator circuit 45 of the mode selector circuit 19. Then, at t₆ whenthe control voltage V_(cc) drops to the reference voltage V₅₂ as at (E)in FIG. 6, the control voltage comparator 51 goes high as at (F) in FIG.6 and remains so by virtue of its own hysteresis until t₇ when thecontrol voltage V_(cc) builds up to the upper trip point (UTP). Thishigh comparator output holds the third switch S₃ of the multiplereference voltage generator circuit 45 off, and its fourth switch S₄ on,from t₆ to t₇.

It is not an absolute necessity that the control voltage comparator 51be hysteretic. This is because the control voltage comparator 51 stayshigh as long as the control voltage V_(cc) is less than the referencevoltage V₅₂. As long as the control voltage comparator 51 is high, thelight load mode may be overridden by the control voltage recovery mode,as from t₆ to t₇ in FIG. 5.

Given herein below is an explanation of how the active switch 7 isdriven at intervals in light load mode and at shorter intervals incontrol voltage recovery mode. The multiple reference voltage generatorcircuit 45 of the mode selector circuit 19 provides the referencevoltage V_(r) that assumes four different values V₁-V₄ in light loadmode and control voltage recovery mode according to the novel principlesof this invention. How the reference voltage V_(r) acquires each of thefour different values V₁-V₄ may be summarized as follows:

1. First value V₁ of the reference voltage V_(r):

The reference voltage V_(r) has the first value V₁ when the output V₄₄from the mode select comparator 44 is high, as from t₂ to t₃ and from t₄to t₅ in FIG. 5, and at the same time when the output V₅₁ from thecontrol voltage comparator 51 is low, as before t₆ in FIG. 5. In otherwords the reference voltage V_(r) has the first value V₁ from the moment(e.g., t₂) the feedback signal V_(f) rises to the fourth referencevoltage value V₄ to the moment (e.g., t₃) the feedback signal V_(f)dwindles to the first reference voltage value V₁, while at the same timethe control voltage V_(cc) is higher than the reference voltage V₅₂.

2. Second value V₂ of the reference voltage V_(r):

The reference voltage V_(r) has the second value V₂ when the output V₄₄from the mode select comparator and the output V₅₁ from the controlvoltage comparator 51 are both high, as from a to b, from c to d, andfrom e to t₇ at (D) in FIG. 5. In other words the reference voltageV_(r) has the second value V₂ while the feedback signal V_(f) drops fromthe third reference voltage value V₃ to the second reference voltagevalue V₂ within the period of t₆, when the control voltage V_(cc) lowersto the reference voltage V₅₂, through t₇, when the control voltage risesback to the UTP.

3. Third value V₃ of the reference voltage V_(r):

The reference voltage V_(r) has the third value V₃ when the output V₅₁from the control voltage comparator 51 is high and at the same time whenthe output V₄₄ from the mode select comparator 44 is low. In other wordsthe reference voltage V_(r) has the third value V₃ while the feedbacksignal V_(f) builds up from the second reference voltage value V₂ to thethird reference voltage value V₃ within the t₆-t₇ period when the outputV₅₁ from the control voltage comparator 51 is high.

4. Fourth value V₄ of the reference voltage V_(r):

The reference voltage V_(r) has the fourth value V₄ when the outputs V₄₄and V₅₁ from the mode select comparator 44 and control voltagecomparator 51 are both low. In other words the reference voltage V_(r)has the fourth value V₄ from the moment (e.g., t₃) the feedback signalV_(f) diminishes to the first reference voltage value V₁ to the moment(e.g., t₄) the feedback signal V_(f) rises back to the fourth referencevoltage value V₄, while at the same time the control voltage V_(cc) ishigher than the reference voltage V₅₂.

The foregoing multiple values of the reference voltage V_(r) affect howthe mode select circuit 19 causes the switch control pulse generatorcircuit 18 to drive the active switch 7. The feedback signal V_(f) atthe junction P₁ of the feedback circuit 39 is constantly higher than thefourth reference voltage value V₄ as long as the power requirement ofthe load 15 is normal, as before t₁ at (C) in FIG. 5. Therefore, asindicated at (D) in FIG. 5, the mode select comparator 44 remains high,holding the first switch S₁ of the multiple reference voltage generatorcircuit 45 closed. The control voltage comparator 51 is now low, as at(F) in FIG. 5, holding the third switch S₃ closed. Thus the referencevoltage V_(r) has the first, and the lowest, value V₁, so that the modeselect comparator 44 is constantly high as at (D) in FIG. 5.

Inputting this high output from the mode select comparator 33, the ANDgate 37 of the switch control pulse generator circuit 18 permits thepassage therethrough of the clock pulses, FIG. 5 (A), from the clock 35on to the flip-flop 36. The clock pulses that have traversed the ANDgate 37 are shown at (B) in FIG. 5 and therein labeled V₃₇. Set by theseclock pulses V₃₇ and reset by the output from the switch controlcomparator 40, the flip-flop 36 delivers the resulting pulses to theswitch driver circuit 38, causing the same to deliver the correspondingswitch control pulses to the active switch 7 over the conductor 24.

Under light load the feedback voltage V_(f) will become less than thatbefore t₁ as at (C) in FIG. 5. The mode select comparator 44 will golow, closing the second switch S₂, when the feedback signal V_(f) dropsto the first reference voltage value V₁. The result will be a change ofthe reference voltage V_(r) to the fourth value V₄, which will hold themode select comparator 44 low. The low output from the mode selectcomparator 44 will disable the AND gate 37, preventing the active switch7 from being driven.

While the active switch 7 is not driven, the control voltage V_(cc) willdiminish whereas the feedback signal V_(f) will rise until it reachesthe fourth reference voltage value V₄ at t₂ as at (C) in FIG. 5.Thereupon the mode select comparator 44 will go high, as at (D) in FIG.5, thereby closing the first switch S₁ and so switching the referencevoltage V_(r) to the first value V₁. As a result, the mode selectcomparator 44 will be hysteretically maintained high from t₂ to t₃, aswill be understood from (C) and (D) in FIG. 5.

The clock pulses from the clock 35 are allowed through the AND gate 37during this t₂-t₃ period, as at (B) in FIG. 5. As the active switch 7 isthus driven, the smoothing capacitor C₁ and C₂, FIG. 1, will both becharged, so that the feedback signal V_(f) will diminish during thisinterval, as at (C) in FIG. 5. Finally, when the feedback signal V_(f)drops to the first reference voltage value V₁ at t₃, the mode selectcomparator 44 will go low as at (D) in FIG. 5, again causing the ANDgate 37 to block the clock pulses. The driving of the active switch 7 isagain suspended at t₃.

When the mode select comparator 44 goes low at t₃ as above, the firstswitch S₁ of the multiple reference voltage generator circuit 45 willturn off, and the second switch S₂ on. The multiple reference voltagegenerator circuit 45 will then put out the reference voltage of thefourth value V₄. The mode select comparator 44 will operatehysteretically, remaining low from t₃ to t₄, as it compares the feedbackvoltage V_(f) with the fourth reference voltage value V₄.

With the active switch 7 left undriven during this t₃-t₄ period, thevoltages across the capacitors C₁ and C₂, FIG. 1, of the rectifying andsmoothing circuit 9 and 10 will diminish whereas the feedback signalV_(f) will build up until it reaches the fourth reference voltage valueV₄ at t₄, as at (C) in FIG. 5. Thereupon the mode select comparator 44will go high and stay so until t₅ as the first switch S₁ turns on, andthe second switch S₂ off, in response to the high output from the modeselect comparator. The operation of the mode select comparator 44 duringthis t₄-t₅ period is identical with that during the t₂-t₃ period.

The active switch 7 is driven at shorter intervals in control voltagerecovery mode according to the novel concepts of this invention.Automatically overriding the light load mode still in progress, thecontrol voltage recovery mode starts at t₆, when the control voltageV_(cc) drops to the LTP of the control voltage comparator 51 as at (E)in FIG. 5, and ends at t₇ when the control voltage rises back to the UTPof the control voltage comparator. As will be understood from (B) inFIG. 5, the active switch 7 is driven at relatively long intervals T₁ inlight load mode, when the control voltage V_(cc) is generally higher,and at shorter intervals T₂ in control voltage recovery mode of thet₆-t₇ period when the control voltage is lower.

The shortening of the drive intervals from the light load mode to thecontrol voltage recovery mode is accomplished by switching the LTP andUTP of the mode select comparator 44 from V₁ and V₄ to V₂ and V₃. Beingboth intermediate the first and fourth reference voltage values V₁ andV₄, the second and third reference voltage values V₂ and V₃ have adifference therebetween that is less than that between the values V₁ andV₄. Thus is the active switch 7 driven at shorter intervals T₂ incontrol voltage recovery mode than those T₁ in light load mode.

FIG. 5 indicates at (F) that the control voltage comparator 51 goes highat t₆ when the control voltage V_(cc) drops to its LTP as at (E). Themode select comparator 44 on the other hand remains low at t₆. Theresults are the closure of the second and fourth switches S₂ and S₄ ofthe multiple reference voltage generator circuit 45, and in consequencethe application of the reference voltage V_(r) of the third value V₃ tothe mode select comparator 44. Then the mode select comparator 44 willsubsequently go high at a when the feedback signal V_(f) rises to thethird reference voltage value V₃ as at (C) in FIG. 15. This high outputfrom the mode select comparator 44 will turn the first switch S₁ on. Thereference voltage V_(r) of the second value V₂ will then be delivered tothe mode select comparator 44 thereby causing the same to remain highuntil b. The clock pulses are therefore free to travel through the ANDgate 37 from a to b, causing the active switch 7 to be driven.

The mode select comparator 44 will go low at b when the feedback signalV_(f) drops to the second reference voltage value V₂ as at (C) in FIG.5. Now the second switch S₂ will turn on, and since the fourth switch S₄has been and is still on, the reference voltage V_(r) of the third valueV₃ will be applied to the mode select comparator 44. This comparator 44will then remain low until c as at (D) in FIG. 5. The clock pulses areblocked by the AND gate 37 from b to c, so that the active switch 7 willbe left undriven.

One cycle of operation has come to an end at c in control voltagerecovery mode. The same cycle will repeat itself thereafter, causing agradual recovery of the control voltage V_(cc) as at (E) in FIG. 5. Att₇, when the control voltage V_(cc) builds up to the UTP of the controlvoltage comparator 51, this comparator will go low, thereby terminatingthe control voltage recovery mode and reinitiating the light load mode.

As has been stated during the assessment of the prior art at thebeginning of this specification, the active switch was drivencontinuously throughout the t₆-t₇ period according to what is believedby this applicant to be the closest prior art. Contrastively, accordingto the instant invention, the active switch is driven intermittently,though of necessity at shorter intervals, in control voltage recoverymode. There are therefore drastically less switchings, and hence lessswitching loss, per unit length of time during the t₆-t₇ period thanheretofore.

It will also be appreciated that there occurs no abnormal drop of thecontrol voltage V_(cc) despite the reduction of switchings per unitlength of time. Fed with the control voltage, the switch control circuit2 will stay in operation, stably driving the active switch 7. The switchcontrol circuit 2 will also continue operation in the face of a certaindrop in the control voltage V_(cc) due to fluctuations in the DC inputvoltage. Thus the invention attains the dual objective of higherefficiency and stable operation in dual-mode switching DC-to-DCconverters.

Embodiment of FIG. 6

Here the invention is applied to a different type of DC-to-DC converterfeaturing a modified DC-to-DC conversion circuit 1 a in which thetransformer 6 has no secondary winding. The first rectifying andsmoothing circuit 9 is connected in parallel with the active switch 7instead of with the transformer secondary as in the first describedembodiment of the invention. This DC-to-DC converter, including theswitch control circuit 2, is akin to that of FIGS. 1 and 2 in all theother details of construction.

In operation, energy will be stored on the inductive transformer primaryN₁ during each conductive period of the active switch 7 when therectifying diode D₁ of the first rectifying and smoothing circuit 9 isreverse biased. The stored energy will be released from the transformerprimary N₁ when the rectifying diode D₁ is subsequently forward biasedupon opening of the active switch 7. Then the smoothing capacitor C₁ ofthe first rectifying and smoothing circuit 9 will be charged with theresultant of the voltage across the power supply 3 and that across thetransformer primary N₁. Thus the DC-to-DC converter incorporates a boostswitching regulator.

The transformer tertiary N₃ is connected as in the FIGS. 1 and 2embodiment to the second rectifying and smoothing circuit 10 whichsupplies the control voltage V_(cc) to the switch control circuit 2.Having the same construction as that in FIG. 2, the switch controlcircuit 2 operates to provide the overriding control voltage recoverymode as required during operation in light load mode.

Embodiment of FIG. 7

A modified mode selector circuit 19 _(a), is shown here for use in theswitch control circuit 2, FIG. 2, in substitution for the mode selectorcircuit 19. The modified mode selector circuit 19, is akin to its FIG. 2counterpart 19 except that the former has a modified multiple referencevoltage generator circuit 45 _(a) in place of its FIG. 2 counterpart 45.

The modified multiple reference voltage generator, circuit 45 _(a) hasfour separate sources 53, 54, 55 and 56 of different reference voltagesV₁, V₂, V₃ and V₄. These reference voltage sources 53-56 are allconnected to the minus input of the mode select comparator 44 viarespective switches 57, 58, 59 and 60, the plus input of the mode selectcomparator being connected to the junction P₁, FIG. 2, of the feedbackcircuit 39 as in the foregoing embodiments of the invention.

The switches 57-60 of the modified multiple reference voltage generatorcircuit 45 _(a) are under the control of AND gates 61, 62, 63 and 64,respectively. The first AND gate 61 has one input connected directly tothe output conductor 28 _(a) of the mode select comparator 44, andanother input connected to the output conductor 27 of the controlvoltage comparator 51, FIG. 2, of the control voltage monitoring circuit20 via a NOT circuit 65. The second AND gate 62 has one input connecteddirectly to the output conductor 28 _(a) of the mode select comparator44, and another input connected directly to the output conductor 27 ofthe control voltage comparator 51. The third AND gate 63 has one inputconnected to the output conductor 28 _(a) of the mode select comparator44 via a NOT circuit 66, and another input connected directly to theoutput conductor 27 of the control voltage comparator 51. The fourth ANDgate 64 has one input connected to the output conductor 28 _(a) of themode select comparator 44 via a NOT circuit 68, and another inputconnected to the output conductor 27 of the control voltage comparator51 via a NOT circuit 67.

Constructed as in the foregoing, the modified multiple reference voltagegenerator circuit 45 _(a) is functionally equivalent to its FIG. 2counterpart 45. A comparison of FIGS. 2 and 7 will reveal that themodified multiple reference voltage generator circuit 45 _(a) puts outthe reference voltage V_(r) of the four different values V₁-V₄ as at (C)in FIG. 5 under the same conditions as does the first disclosed circuit45.

Embodiment of FIGS. 8 and 9

At 70 in FIG. 8 is shown a sawtooth generator circuit which may beadopted in lieu of the current detect resistor 8, FIG. 1. As will berecalled by referring back to both FIGS. 1 and 2, the current detectresistor 8 provides the sawtoothed current detect signal V_(i), seen at(E) in both FIGS. 3 and 4, for application to the switch controlcomparator 40 as in FIG. 2. The sawtooth generator circuit 70 comprisesa capacitor C having one terminal coupled to a DC supply terminal +V viaa resistor R, and another terminal grounded. A switch SW is connected inparallel with the capacitor C and has a control input connected to theinverting output of the RS flip-flop 36.

As the switch SW is turned on and off by the output, FIG. 9 (A), fromthe flip-flop 36, the capacitor C will be charged from the supplyterminal +V in synchronism with the closure of the active switch 7,FIG. 1. Thus the sawtooth generator circuit 70 provides a ramp voltagesignal V_(c), FIG. 9 (B), for application to the plus input of theswitch control comparator 40. Each time the ramp voltage V_(c) reachesthe feedback signal V_(f), the switch control comparator 40 will resetthe flip-flop 36 and thereby cause the switch SW to turn on. Thecapacitor C will then discharge.

Possible Modifications

Notwithstanding the foregoing detailed disclosure it is not desired thatthe present invention be limited by the exact showing of the drawings orthe description thereof. The following is a brief list of possiblemodifications, alterations or adaptations of the illustrated embodimentswhich are all believed to fall within the purview of this invention:

1. The invention is adaptable for a variety of DC-to-DC converters eachhaving one or more active switches to be controlled, other than thatdesignated 1 in FIG. 1. Examples include a forward DC-to-DC converter, ahalf-bridge DC-to-DC converter having a pair of active switches, amodified half-bridge DC-to-DC converter, a combination of a bridgeinverter circuit, with four active switches in bridge connection, and arectifying and smoothing circuit on the output stage of the invertercircuit, and a combination of a push-pull inverter, having two activeswitches and a transformer, and a rectifying and smoothing circuit.

2. The active switch 7 could be driven at a rate that varies with thepower requirement of the load.

3. The mode select comparator 44, FIG. 2, of the mode selector circuit19 is replaceable by a hysteretic comparator for combined use with asingle reference voltage source instead of the multiple referencevoltage generator circuit 45 Another circuit will then be required foraltering the range of hysteretic operation of the comparator accordingto the output V₅₁, FIG. 5 (F), from the control voltage comparator 51.

4. The active switch 7 could take the form of controllable solid-stateswitches other than the FET, such as a bipolar transistor and aninsulated-gate bipolar transistor.

5. The output voltage detector circuit 17, FIG. 1, and switch controlpulse generator circuit 18 may be coupled together electrically insteadof via the opto-couplers in cases where such an isolation mechanism isnot required.

6. Logic circuits such as the AND gate 37, FIG. 2, are replaceable byother equivalent means.

7. The current detect resistor 8 is replaceable by other means such as aHall generator or like magneto-electric converter.

8. The mode selector circuit 19 is modifiable to rely on the currentdetect signal V_(i), rather than on the feedback signal V_(f), todetermine the power requirement of the load.

9. As indicated by the dashed lines in FIG. 2, the AND gate 37 could beconnected between flip-flop 36 and switch driver circuit 38, with thetwo inputs of the AND gate connected respectively to the flip-flop 36and to the mode select comparator 44. The clock pulses might then be feddirectly into the flip-flop 36.

1. A dual-mode switching DC-to-DC converter capable of operation ineither normal load mode or light load mode depending upon the powerrequirement of a load, the DC-to-DC converter having an active switchconnected to DC input means via a transformer, a switch control circuitfor controllably driving the active switch, a first rectifying andsmoothing circuit connected between the transformer and DC output meansfor providing a DC output voltage to be applied to a load, and a secondrectifying and smoothing circuit connected between the transformer andthe switch control circuit for providing a control voltage to be fed tothe switch control circuit for powering the same, wherein theimprovement resides in the switch control circuit comprising: (a)feedback circuit means for providing a feedback signal indicative of theDC output voltage; (b) a control voltage monitoring circuit connected tothe second rectifying and smoothing circuit for providing an outputsignal indicative of whether the control voltage is less than apredefined limit or not; (c) a switch control pulse generator circuitconnected between the feedback circuit means and the active switch forgenerating switch control pulses thereby to drive the active switch soas to keep the DC output voltage constant; (d) a multiple referencevoltage generator circuit connected to the control voltage monitoringcircuit for providing a multiple-value reference signal that has eitherof first two different predefined values when the control voltage is notless than the predefined limit and that has either of second twodifferent predefined values when the control voltage is less than thepredefined limit, the second two different predefined values beingintermediate the first two different predefined values; and (e) a modeselect comparator having a first input connected to the feedback circuitmeans, a second input connected to the multiple reference voltagegenerator circuit, and an output connected to the switch control pulsegenerator circuit.
 2. A dual-mode switching DC-to-DC converter asdefined in claim 1, wherein the multiple reference voltage generatorcircuit comprises: (a) means for generating a first reference voltagevalue when the control voltage is not less than the predefined limit;(b) means for generating a second reference voltage value, which ishigher than the first reference voltage value, when the control voltageis less than the predefined limit; (c) means for generating a thirdreference voltage value, which is higher than the second referencevoltage value, when the control voltage is less than the predefinedlimit; and (d) means for generating a fourth reference voltage value,which is higher than the third reference voltage value, when the controlvoltage is not less than the predefined limit.
 3. A dual-mode switchingDC-to-DC converter as defined in claim 1, wherein the multiple referencevoltage generator circuit comprises: (a) a serial circuit of a firstswitch and a first resistor and a first reference voltage sourceconnected to the second input of the mode select comparator, the firstswitch being closed when the active switch is being driven; (b) a serialcircuit of a second switch and a second resistor and a second referencevoltage source connected to the second input of the mode selectcomparator, the second switch being closed when the active switch is notbeing driven; (c) a serial circuit of a third switch and a thirdresistor connected in parallel with the serial circuit of the firstresistor and the first reference voltage source, the third switch beingclosed when the control voltage is not less than the predefined limit;and (d) a serial circuit of a fourth switch and a fourth resistorconnected in parallel with the serial circuit of the second resistor andthe second reference voltage source, the fourth switch being closed whenthe control voltage is less than the predefined limit.
 4. A dual-modeswitching DC-to-DC converter as defined in claim 1, wherein thepredefined limit of the control voltage from the second rectifying andsmoothing circuit is less than a rated output voltage of the secondrectifying and smoothing circuit and not less than a minimum voltage atwhich the switch control circuit is maintained in operation.
 5. Adual-mode switching DC-to-DC converter as defined in claim 1, whereinthe switch control pulse generator circuit of the switch control circuitcomprises: (a) ramp generating means for generating a ramp signal insynchronism with the conducting periods of the active switch; (b) aswitch control comparator connected to the feedback means and the rampgenerating means for comparing the feedback signal and the ramp signal;(c) a source of clock pulses; (d) a logic circuit having one inputconnected to the clock pulse source and another input connected to themode select comparator for selectively blocking the clock pulses asrequired by the mode select comparator; (e) an RS flip-flop having oneinput connected to the logic circuit and another input connected to theswitch control comparator; and (f) a switch driver connected between theflip-flop and the active switch for driving the latter in response to anoutput from the former.
 6. A dual-mode switching DC-to-DC converter asdefined in claim 1, wherein the switch control pulse generator circuitof the switch control circuit comprises: (a) ramp generating means forgenerating a ramp signal in synchronism with the conducting periods ofthe active switch; (b) a switch control comparator connected to thefeedback means and the ramp generating means for comparing the feedbacksignal and the ramp signal; (c) a source of clock pulses; (d) an RSflip-flop having one input connected to the clock pulse source andanother input connected to the switch control comparator; (e) a logiccircuit having one input connected to the flip-flop and another inputconnected to the mode select comparator for selectively blocking theclock pulses as required by the mode select comparator; and (f) a switchdriver connected between the flip-flop and the active switch for drivingthe latter in response to an output from the former.